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ISCA
2008
IEEE
112views Hardware» more  ISCA 2008»
15 years 10 months ago
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
In a chip-multiprocessor (CMP) system, the DRAM system is shared among cores. In a shared DRAM system, requests from a thread can not only delay requests from other threads by cau...
Onur Mutlu, Thomas Moscibroda
ISCA
2006
IEEE
154views Hardware» more  ISCA 2006»
15 years 10 months ago
SODA: A Low-power Architecture For Software Radio
The physical layer of most wireless protocols is traditionally implemented in custom hardware to satisfy the heavy computational requirements while keeping power consumption to a ...
Yuan Lin, Hyunseok Lee, Mark Woh, Yoav Harel, Scot...
ATAL
2005
Springer
15 years 9 months ago
Exploiting belief bounds: practical POMDPs for personal assistant agents
Agents or agent teams deployed to assist humans often face the challenges of monitoring the state of key processes in their environment (including the state of their human users t...
Pradeep Varakantham, Rajiv T. Maheswaran, Milind T...
SEAL
1998
Springer
15 years 8 months ago
Automating Space Allocation in Higher Education
The allocation of office space in any large institution is usually a problematical issue, which often demands a substantial amount of time to perform manually. The result of this a...
Edmund K. Burke, D. B. Varley
126
Voted
AAAI
2010
15 years 5 months ago
PUMA: Planning Under Uncertainty with Macro-Actions
Planning in large, partially observable domains is challenging, especially when a long-horizon lookahead is necessary to obtain a good policy. Traditional POMDP planners that plan...
Ruijie He, Emma Brunskill, Nicholas Roy
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