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ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
15 years 2 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...
ICIP
2010
IEEE
14 years 7 months ago
Undecimated haar thresholding for poisson intensity estimation
We propose a novel algorithm for denoising Poisson-corrupted images, that performs a signal-adaptive thresholding of the undecimated Haar wavelet coefficients. A Poisson's un...
Florian Luisier, Thierry Blu, Michael Unser
FSE
1997
Springer
131views Cryptology» more  FSE 1997»
15 years 1 months ago
Fast Software Encryption: Designing Encryption Algorithms for Optimal Software Speed on the Intel Pentium Processor
Most encryption algorithms are designed without regard to their performance on top-of-the-line microprocessors. This paper discusses general optimization principles algorithms desi...
Bruce Schneier, Doug Whiting
ISPAN
2002
IEEE
15 years 2 months ago
Automatic Processor Lower Bound Formulas for Array Computations
In the directed acyclic graph (dag) model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations: Given a sequenc...
Peter R. Cappello, Ömer Egecioglu
FMSD
2002
107views more  FMSD 2002»
14 years 9 months ago
Verification of Out-Of-Order Processor Designs Using Model Checking and a Light-Weight Completion Function
We present a new technique for verification of complex hardware devices that allows both generality andahighdegreeofautomation.Thetechniqueisbasedonournewwayofconstructinga"li...
Sergey Berezin, Edmund M. Clarke, Armin Biere, Yun...