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» An address translation simulator
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DATE
2005
IEEE
187views Hardware» more  DATE 2005»
15 years 3 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
80
Voted
DI
2007
81views more  DI 2007»
14 years 9 months ago
Using every part of the buffalo in Windows memory analysis
All Windows memory analysis techniques depend on the examiner’s ability to translate the virtual addresses used by programs and operating system components into the true locatio...
Jesse D. Kornblum
VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
15 years 10 months ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
BIRTHDAY
2005
Springer
15 years 3 months ago
Simulating Algebraic High-Level Nets by Parallel Attributed Graph Transformation
The “classical” approach to represent Petri nets by graph transformation systems is to translate each transition of a specific Petri net to a graph rule (behavior rule). This ...
Claudia Ermel, Gabriele Taentzer, Roswitha Bardohl
EMNLP
2004
14 years 11 months ago
Adaptive Language and Translation Models for Interactive Machine Translation
We describe experiments carried out with adaptive language and translation models in the context of an interactive computer-assisted translation program. We developed cache-based ...
Laurent Nepveu, Guy Lapalme, Philippe Langlais, Ge...