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SLIP
2003
ACM
15 years 2 months ago
Error-correction and crosstalk avoidance in DSM busses
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
Ketan N. Patel, Igor L. Markov
PATMOS
2004
Springer
15 years 2 months ago
Physical Extension of the Logical Effort Model
Abstract. The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the...
B. Lasbouygues, Robin Wilson, Philippe Maurine, Na...
GECCO
2010
Springer
162views Optimization» more  GECCO 2010»
15 years 2 months ago
Heuristics for sampling repetitions in noisy landscapes with fitness caching
For many large-scale combinatorial search/optimization problems, meta-heuristic algorithms face noisy objective functions, coupled with computationally expensive evaluation times....
Forrest Stonedahl, Susa H. Stonedahl
JDWM
2006
178views more  JDWM 2006»
14 years 9 months ago
Improved Data Partitioning for Building Large ROLAP Data Cubes in Parallel
The pre-computation of data cubes is critical to improving the response time of On-Line Analytical Processing (OLAP) systems and can be instrumental in accelerating data mining ta...
Ying Chen, Frank K. H. A. Dehne, Todd Eavis, Andre...
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ISVLSI
2007
IEEE
184views VLSI» more  ISVLSI 2007»
15 years 3 months ago
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the m...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu