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RTCSA
2006
IEEE
15 years 10 months ago
Instruction Scheduling with Release Times and Deadlines on ILP Processors
ILP (Instruction Level Parallelism) processors are being increasingly used in embedded systems. In embedded systems, instructions may be subject to timing constraints. An optimisi...
Hui Wu, Joxan Jaffar, Jingling Xue
ASPLOS
2008
ACM
15 years 6 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August
DAC
2006
ACM
16 years 5 months ago
Architecture-aware FPGA placement using metric embedding
Since performance on FPGAs is dominated by the routing architecture rather than wirelength, we propose a new architecture-aware approach to initial FPGA placement that models the ...
Padmini Gopalakrishnan, Xin Li, Lawrence T. Pilegg...
PAMI
2010
207views more  PAMI 2010»
14 years 11 months ago
Document Ink Bleed-Through Removal with Two Hidden Markov Random Fields and a Single Observation Field
We present a new method for blind document bleed through removal based on separate Markov Random Field (MRF) regularization for the recto and for the verso side, where separate pri...
Christian Wolf
INFOCOM
2005
IEEE
15 years 9 months ago
Joint congestion control and media access control design for ad hoc wireless networks
Abstract— We present a model for the joint design of congestion control and media access control (MAC) for ad hoc wireless networks. Using contention graph and contention matrix,...
Lijun Chen, Steven H. Low, John C. Doyle