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112
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ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
15 years 7 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
104
Voted
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
15 years 3 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
VLSID
2002
IEEE
136views VLSI» more  VLSID 2002»
15 years 10 months ago
Buffered Routing Tree Construction under Buffer Placement Blockages
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
Wei Chen, Massoud Pedram, Premal Buch
IPPS
2005
IEEE
15 years 3 months ago
MaTCH : Mapping Data-Parallel Tasks on a Heterogeneous Computing Platform Using the Cross-Entropy Heuristic
We propose in this paper a heuristic for mapping a set of interacting tasks of a parallel application onto a heterogeneous computing platform such as a computational grid. Our nov...
Soumya Sanyal, Sajal K. Das
83
Voted
FPGA
2005
ACM
80views FPGA» more  FPGA 2005»
15 years 3 months ago
Simultaneous timing-driven placement and duplication
Logic duplication is an effective method for improving circuit performance. In this paper we present an algorithm named SPD that performs simultaneous placement and duplication to...
Gang Chen, Jason Cong