Sciweavers

58 search results - page 9 / 12
» An alternative QoS architecture for the IEEE 802.16 standard
Sort
View
ICCD
2002
IEEE
135views Hardware» more  ICCD 2002»
15 years 8 months ago
Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
Luca Benini, Davide Bertozzi, Davide Bruni, Nicola...
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
15 years 6 months ago
Compact hardware design of Whirlpool hashing core
Weaknesses have recently been found in the widely used cryptographic hash functions SHA-1 and MD5. A potential alternative for these algorithms is the Whirlpool hash function, whi...
Timo Alho, Panu Hämäläinen, Marko H...
FPT
2005
IEEE
133views Hardware» more  FPT 2005»
15 years 5 months ago
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...
INFOCOM
2007
IEEE
15 years 6 months ago
Optimal-Complexity Optical Router
—In the past years, electronic routers have had trouble keeping up with the increase in optical fiber capacity. As their power consumption has grown exponentially and already ex...
Hadas Kogan, Isaac Keslassy
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
15 years 6 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...