- We present an architecture for data streams based on structures typically found in web cache hierarchies. The main idea is to build a meta level analyser from a number of levels ...
Geoffrey Holmes, Bernhard Pfahringer, Richard Kirk...
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
In main-memory databases, the number of processor cache misses has a critical impact on the performance of the system. Cacheconscious indices are designed to improve performance b...
Chip Multiprocessors (CMPs) allow different applications to concurrently execute on a single chip. When applications with differing demands for memory compete for a shared cache, ...
Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qu...
We propose and analyze an information-sharing application for wireless intervehicular networks, called Infoshare. Infoshare leverages the broadcast nature of the wireless medium t...
Marco Fiore, Claudio Casetti, Carla-Fabiana Chiass...