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FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
15 years 4 months ago
A Scalable FPGA-based Multiprocessor
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
Arun Patel, Christopher A. Madill, Manuel Salda&nt...
JNCA
2011
126views more  JNCA 2011»
14 years 5 months ago
Coordinated session-based admission control with statistical learning for multi-tier internet applications
Popular Internet applications deploy a multi-tier architecture, with each tier provisioning a certain functionality to its preceding tier. In this paper, we address the challengin...
Sireesha Muppala, Xiaobo Zhou
ARCS
2004
Springer
15 years 3 months ago
A Comparison of Parallel Programming Models of Network Processors
: Today’s network processor utilize parallel processing in order to cope with the traffic growth and wire-speed of current and future network technologies. In this paper, we stu...
Carsten Albrecht, Rainer Hagenau, Erik Maehle, And...
ITIIS
2010
158views more  ITIIS 2010»
14 years 5 months ago
Development of a Dynamic Collision Avoidance Algorithm for Indoor Tracking System Based on Active RFID
We propose a novel collision-avoidance algorithm for the active type RFID regarding an indoor tracking system. Several well-known collision avoidance algorithms are analyzed consi...
Sekyung Han, Yeonsuk Choi, Masayuki Iwai, Kaoru Se...
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CODES
2006
IEEE
15 years 4 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt