149 search results - page 4 / 30 » An approach for implementing efficient superscalar CISC proc... |
ASPLOS
2006
ACM
15 years 3 months ago
2006
ACM
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
MICRO
1996
IEEE
15 years 1 months ago
1996
IEEE
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
ICMCS
2006
IEEE
15 years 3 months ago
2006
IEEE
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
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ISJGP
2010
14 years 6 months ago
2010
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
ISCA
2007
IEEE
15 years 3 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...