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» An architecture and algorithms for multi-run clustering
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DSN
2003
IEEE
15 years 5 months ago
Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology
Arbitrary faults of a single node in a time-triggered architecture (TTA) bus topology system may cause error propagation to correct nodes and may lead to inconsistent system state...
Astrit Ademaj, Håkan Sivencrona, Günthe...
CORR
2007
Springer
109views Education» more  CORR 2007»
14 years 11 months ago
Self-Organising management of Grid environments
: This paper presents basic concepts, architectural principles and algorithms for efficient resource and security management in cluster computing environments and the Grid. The wor...
Ioannis Liabotis, Ognjen Prnjat, Temitope Olukemi,...
DAC
2001
ACM
16 years 19 days ago
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping
In this paper, we study the problem of performance-driven multi-level circuit clustering with application to hierarchical FPGA designs. We first show that the performance-driven m...
Jason Cong, Michail Romesis
CHI
2008
ACM
16 years 2 days ago
AutoCardSorter: designing the information architecture of a web site using latent semantic analysis
In this paper, we describe an innovative tool that supports the design and evaluation of the information architecture of a Web site. The tool uses Latent Semantic Analysis and hie...
Christos Katsanos, Nikolaos K. Tselios, Nikolaos M...
CIIA
2009
15 years 23 days ago
Physical Synthesis for CPLD Architectures
In this paper, we present a new synthesis feature namely, "Xor matching", and the foldback product term synthesis for Complex Programmable Logic Devices (CPLD) architectu...
Sid-Ahmed Senouci