24 search results - page 3 / 5 » An area-optimality study of floorplanning |
ISVLSI
2006
IEEE
14 years 9 days ago
2006
IEEE
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
ASPDAC
2005
ACM
13 years 8 months ago
2005
ACM
- By putting different chips on the same mask, shuttle mask (or multiple project wafer) provides an economical solution for low volume designs and design prototypes to share the ri...
ICCD
2001
IEEE
14 years 3 months ago
2001
IEEE
Classical floorplanning minimizes a linear combination of area and wirelength. When Simulated Annealing is used, e.g., with the Sequence Pair representation, the typical choice o...
ISPASS
2006
IEEE
14 years 9 days ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
SIGMOD
2007
ACM
14 years 6 months ago
2007
ACM
We present a tool for querying a set of points for geometric shapes. This tool was developed as part of a larger project studying the architecture of 13th century French churches....