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DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
15 years 6 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
15 years 6 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper
SI3D
2003
ACM
15 years 5 months ago
Shear-image order ray casting volume rendering
This paper describes shear-image order ray casting, a new method for volume rendering. This method renders sampled data in three dimensions with image quality equivalent to the be...
Yin Wu, Vishal Bhatia, Hugh C. Lauer, Larry Seiler
GIS
2004
ACM
16 years 25 days ago
A partial join approach for mining co-location patterns
Spatial co-location patterns represent the subsets of events whose instances are frequently located together in geographic space. We identified the computational bottleneck in the...
Jin Soung Yoo, Shashi Shekhar
AGP
2003
IEEE
15 years 3 months ago
Advanced Backjumping Techniques for Rule Instantiations
Abstract. The interest in the area of non-monotonic reasoning and declarative logic programming is growing rapidly after the recent development of a number of Answer Set Programmin...
Simona Perri, Francesco Scarcello