301 search results - page 1 / 61 » An efficient algorithm to verify generalized false paths |
118
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DAC
2010
ACM
15 years 9 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
160
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ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
Due to false paths and multi-cycle paths in a circuit, using only topological delay to determine the clock period could be too conservative. In this paper, we address the timing a...
127
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DAC
2002
ACM
16 years 6 months ago
2002
ACM
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
132
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ICCAD
1994
IEEE
15 years 9 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
138
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SPAA
2005
ACM
15 years 10 months ago
2005
ACM
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...