75 search results - page 1 / 15 » An efficient approach to simultaneous transistor and interco... |
72
Voted
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...
ISPD
1998
ACM
15 years 1 months ago
1998
ACM
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
ISPD
2004
ACM
15 years 3 months ago
2004
ACM
Considering the voltage drop constraint over a distributed model for power/ground (P/G) network, we study the following two problems for physical synthesis of sleep transistors: t...
DAC
1999
ACM
15 years 1 months ago
1999
ACM
We present a new approach for estimation and optimization of the average stand-by power dissipation in large MOS digital circuits. To overcome the complexity of state dependence i...