110 search results - page 4 / 22 » An efficient verification algorithm for parallel controllers |
84
Voted
HASE
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper deals with verification of flow control in concurrent programs. We use Ada language model as reference. After translation of Ada programs into Petri nets (named Ada net...
FORMATS
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. We describe a partial order reduction technique for a realtime component model. Components are described as timed automata with data ports, which can be composed in stati...
RTSS
1996
IEEE
15 years 1 months ago
1996
IEEE
We propose a method for reducing the number of clocks of a timed automaton by combining two algorithms. The first one consists in detecting active clocks, that is, those clocks wh...
DAC
2005
ACM
15 years 10 months ago
2005
ACM
SAT (Boolean satisfiability) has become the primary Boolean reasoning engine for many EDA applications, so the efficiency of SAT solving is of great practical importance. Recently...
FTDCS
1997
IEEE
15 years 1 months ago
1997
IEEE
Though causal order of message delivery simplifies the design and development of distributed applications, the overhead of enforcing it is not negligible. Causal order algorithm w...