63 search results - page 6 / 13 » An embedded true random number generator for FPGAs |
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In spite of the high parallelism exhibited by cellular automata architectures, most implementations are usually run in software. For increasing execution parallelism, hardware imp...
CAI
2004
Springer
14 years 9 months ago
2004
Springer
A complete hardware implementation of an evolvable combinational unit for FPGAs is presented. The proposed combinational unit consisting of a virtual reconfigurable circuit and evo...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected b...
RSA
2008
14 years 9 months ago
2008
We present an expected polynomial time algorithm to generate an unlabeled connected cubic planar graph uniformly at random. We first consider rooted connected cubic planar graphs, ...
APPROX
2008
Springer
14 years 11 months ago
2008
Springer
Let H be a graph, and let CH(G) be the number of (subgraph isomorphic) copies of H contained in a graph G. We investigate the fundamental problem of estimating CH(G). Previous res...