2488 search results - page 154 / 498 » An improvement in formal verification |
DAC
2003
ACM
16 years 2 months ago
2003
ACM
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
202
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POPL
2007
ACM
16 years 1 months ago
2007
ACM
We present a formal model of memory that both captures the lowlevel features of C's pointers and memory, and that forms the basis for an expressive implementation of separati...
CHARME
2003
Springer
15 years 4 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
120
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EPK
2006
15 years 2 months ago
2006
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
109
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CACM
2010
14 years 10 months ago
2010
Certified software consists of a machine-executable program plus a formal machine-checkable proof that the software is free of bugs with respect to a claim of dependability. The c...