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» An improvement in formal verification
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ECRTS
1998
IEEE
15 years 5 months ago
Tool-supported hierarchical design of distributed real-time systems
In this paper we demonstrate the usage of a formal description technique for real-time systems called PLCAutomaton [4] by applying this method to a real-world case study. To this ...
Henning Dierks, Josef Tapken
CCS
2006
ACM
15 years 5 months ago
An intruder model for verifying liveness in security protocols
We present a process algebraic intruder model for verifying a class of liveness properties of security protocols. For this class, the proposed intruder model is proved to be equiv...
Jan Cederquist, Muhammad Torabi Dashti
FMCAD
2000
Springer
15 years 4 months ago
Checking Safety Properties Using Induction and a SAT-Solver
We take a fresh look at the problem of how to check safety properties of finite state machines. We are particularly interested in checking safety properties with the help of a SAT-...
Mary Sheeran, Satnam Singh, Gunnar Stålmarck
ROOM
2000
15 years 2 months ago
Structured Axiomatic Semantics for UML Models
In this paper we provide a systematic formal interpretation for most elements of the UML notation. This interpretation, in a structured temporal logic, enables precise analysis of...
Kevin Lano, Juan Bicarregui, Andy Evans
FMICS
2010
Springer
15 years 1 months ago
Range Analysis of Microcontroller Code Using Bit-Level Congruences
Bitwise instructions, loops and indirect data access pose difficult challenges to the verification of microcontroller programs. In particular, it is necessary to show that an indir...
Jörg Brauer, Andy King, Stefan Kowalewski