2488 search results - page 214 / 498 » An improvement in formal verification |
HPCA
2003
IEEE
16 years 1 months ago
2003
IEEE
Due to cost, time, and flexibility constraints, simulators are often used to explore the design space when developing a new processor architecture, as well as when evaluating the ...
SIGSOFT
2003
ACM
15 years 6 months ago
2003
ACM
Model checking and other finite-state analysis techniques have been very successful when used with hardware systems and less successful with software systems. It is especially di...
123
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RTAS
2009
IEEE
15 years 8 months ago
2009
IEEE
Embedded systems in safety-critical environments demand safety guarantees while providing many useful services that are too complex to formally verify or fully test. Existing appl...
102
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FM
2001
Springer
15 years 5 months ago
2001
Springer
To develop efficient algorithms for the reachability analysis of timed automata, a promising approach is to use binary decision diagrams (BDDs) as data structure for the representa...
141
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FM
2008
Springer
15 years 2 months ago
2008
Springer
Abstract. The Java Modeling Language (JML) recently switched to an assertion semantics based on "strong validity" in which an assertion is taken to be valid precisely whe...