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» An improvement in formal verification
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PDP
2007
IEEE
15 years 7 months ago
Improving the Development Process for CSE Software
Scientific and engineering programming has been around since the beginning of computing, often being the driving force for new system development and innovation. At the same time...
Michael A. Heroux, James M. Willenbring, Michael N...
ASPDAC
2005
ACM
117views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Dynamic symmetry-breaking for improved Boolean optimization
With impressive progress in Boolean Satisfiability (SAT) solving and several extensions to pseudo-Boolean (PB) constraints, many applications that use SAT, such as highperformanc...
Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Kare...
CAV
2009
Springer
157views Hardware» more  CAV 2009»
16 years 1 months ago
Explaining Counterexamples Using Causality
Abstract. When a model does not satisfy a given specification, a counterexample is produced by the model checker to demonstrate the failure. A user must then examine the counterexa...
Ilan Beer, Shoham Ben-David, Hana Chockler, Avigai...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 1 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
POPL
2005
ACM
16 years 1 months ago
Downgrading policies and relaxed noninterference
In traditional information-flow type systems, the security policy is often formalized as noninterference properties. However, noninterference alone is too strong to express securi...
Peng Li, Steve Zdancewic