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» An improvement in formal verification
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ATAL
2010
Springer
15 years 1 months ago
Verifying agents with memory is harder than it seemed
ATL+ is a variant of alternating-time temporal logic that does not have the expressive power of full ATL , but still allows for expressing some natural properties of agents. It ha...
Nils Bulling, Wojciech Jamroga
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
15 years 1 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
JUCS
2008
166views more  JUCS 2008»
15 years 1 months ago
ASM Refinement Preserving Invariants
: This paper gives a definition of ASM refinement suitable for the verification that a protocol implements atomic transactions. We used this definition as the basis of the formal v...
Gerhard Schellhorn
CASES
2010
ACM
14 years 11 months ago
Instruction selection by graph transformation
Common generated instruction selections are based on tree pattern matching, but modern and custom architectures feature instructions, which cannot be covered by trees. To overcome...
Sebastian Buchwald, Andreas Zwinkau
SIGSOFT
2010
ACM
14 years 11 months ago
Software economies
Software construction has typically drawn on engineering metaphors like building bridges or cathedrals, which emphasize architecture, specification, central planning, and determin...
David F. Bacon, Eric Bokelberg, Yiling Chen, Ian A...