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» An improvement in formal verification
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DATE
2000
IEEE
132views Hardware» more  DATE 2000»
15 years 5 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ICCAD
1998
IEEE
80views Hardware» more  ICCAD 1998»
15 years 5 months ago
On the optimization power of retiming and resynthesis transformations
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a de...
Rajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, R...
HASE
2007
IEEE
15 years 5 months ago
Multiple Pre/Post Specifications for Heap-Manipulating Methods
Automated verification plays an important role for high assurance software. This typically uses a pair of pre/post conditions as a formal (but possibly partial) specification of e...
Wei-Ngan Chin, Cristina David, Huu Hai Nguyen, She...
APSEC
2004
IEEE
15 years 5 months ago
The Design of Evolutionary Process Modeling Languages
To formalize a software process, its important aspects must be extracted as a model. Many processes are used repeatedly, and the ability to automate a process is also desired. One...
Darren C. Atkinson, Daniel C. Weeks, John Noll
CAV
2006
Springer
128views Hardware» more  CAV 2006»
15 years 5 months ago
Safraless Compositional Synthesis
In automated synthesis, we transform a specification into a system that is guaranteed to satisfy the specification. In spite of the rich theory developed for system synthesis, litt...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi