2488 search results - page 283 / 498 » An improvement in formal verification |
DAC
2000
ACM
16 years 2 months ago
2000
ACM
We recently introduced symbolic timing simulation (STS) using data-dependent delays as a tool for verifying the timing of fullcustom transistor-level circuit designs, and for the ...
DAC
2005
ACM
16 years 2 months ago
2005
ACM
We present several improvements to general-purpose sequential redundancy removal. First, we propose using a robust variety of synergistic transformation and verification algorithm...
101
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COST
2009
Springer
15 years 8 months ago
2009
Springer
Nowadays biometrics becomes an important field in IT security, safety and comfort research for automotive. Aims are automatic driver authentication or recognition of spoken command...
125
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
Simulation of transaction level models (TLMs) is an established embedded systems design technique. Its use cases include virtual prototyping for early software development, platfo...
104
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CCS
2007
ACM
15 years 7 months ago
2007
ACM
Static analysis tools can handle large-scale software and find thousands of defects. But do they improve software security? We evaluate the effect of static analysis tool use on s...