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» An improvement in formal verification
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82
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FMCAD
2006
Springer
15 years 4 months ago
Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip
Claude Helmstetter, Florence Maraninchi, Laurent M...
75
Voted
DATE
2006
IEEE
96views Hardware» more  DATE 2006»
15 years 6 months ago
A methodology for FPGA to structured-ASIC synthesis and verification
Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden a...
Michael Hutton, Richard Yuan, Jay Schleicher, Greg...
95
Voted
SIGSOFT
2010
ACM
14 years 7 months ago
Language-based verification will change the world
We argue that lightweight, language-based verification is poised to enter mainstream industrial use, where it will have a major impact on software quality and reliability. We expl...
Tim Sheard, Aaron Stump, Stephanie Weirich
122
Voted
PPOPP
2010
ACM
15 years 10 months ago
GAMBIT: effective unit testing for concurrency libraries
As concurrent programming becomes prevalent, software providers are investing in concurrency libraries to improve programmer productivity. Concurrency libraries improve productivi...
Katherine E. Coons, Sebastian Burckhardt, Madanlal...
SPLC
2004
15 years 2 months ago
A Methodology for the Derivation and Verification of Use Cases for Product Lines
In this paper, we present a methodology to express, in a formal way, the requirements of products belonging to a product line. We relied on a formalism allowing the representation ...
Alessandro Fantechi, Stefania Gnesi, Giuseppe Lami...