2488 search results - page 90 / 498 » An improvement in formal verification |
99
Voted
ACSC
2004
IEEE
15 years 4 months ago
2004
IEEE
This paper introduces a repeatable and constructive approach to the analysis of loop progress and termination conditions in imperative programs. It is applicable to all loops for ...
114
Voted
FM
2009
Springer
14 years 10 months ago
2009
Springer
Abstract. This paper presents a Rewriting Logic framework that formalizes the interactions between Web servers and Web browsers through icating protocol abstracting HTTP. The propo...
101
Voted
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
15 years 5 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
100
Voted
CSL
2004
Springer
15 years 4 months ago
2004
Springer
Using separation logic, this paper presents three Hoare logics (corresponding to different notions of correctness) for the simple While language extended with commands for heap acc...
99
Voted
CADE
2007
Springer
16 years 1 months ago
2007
Springer
In this paper, a proof assistant, called SAD, is presented. SAD deals with mathematical texts that are formalized in the ForTheL language (brief description of which is also given)...