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» An integrated GPU power and performance model
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CF
2004
ACM
15 years 7 months ago
Integrated temporal and spatial scheduling for extended operand clustered VLIW processors
Centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption and are thus not suitable for consumer electronic devices. The conse...
Rahul Nagpal, Y. N. Srikant
118
Voted
DAC
2002
ACM
16 years 2 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
125
Voted
VTC
2007
IEEE
15 years 8 months ago
Discrete Power Allocation for Lifetime Maximization in Cooperative Networks
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
Wan-Jen Huang, Yao-Win Hong, C. C. Jay Kuo
ISLPED
2005
ACM
108views Hardware» more  ISLPED 2005»
15 years 7 months ago
Replacing global wires with an on-chip network: a power analysis
This paper explores the power implications of replacing global chip wires with an on-chip network. We optimize network links by varying repeater spacing, link pipelining, and volt...
Seongmoo Heo, Krste Asanovic
122
Voted
CORR
2006
Springer
189views Education» more  CORR 2006»
15 years 1 months ago
Node-Based Optimal Power Control, Routing, and Congestion Control in Wireless Networks
Abstract--In wireless networks, important network functionalities such as power control, rate allocation, routing, and congestion control must be optimized in a coherent and integr...
Yufang Xi, Edmund M. Yeh