260 search results - page 20 / 52 » An integrated GPU power and performance model |
115
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ASPDAC
2008
ACM
15 years 3 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
127
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ICCAD
2004
IEEE
15 years 10 months ago
2004
IEEE
— Cycle-accurate functional descriptions (CAFDs) are being widely adopted in integrated circuit (IC) design flows. Power estimation can potentially benefit from the inherent in...
120
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DAC
2005
ACM
15 years 3 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
102
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CASES
2004
ACM
15 years 7 months ago
2004
ACM
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
148
Voted
DEBS
2010
ACM
15 years 5 months ago
2010
ACM
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...