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» An integrated GPU power and performance model
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99
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DAC
2005
ACM
16 years 2 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
15 years 7 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
108
Voted
NAR
2010
123views more  NAR 2010»
14 years 8 months ago
Xenbase: gene expression and improved integration
Xenbase (www.xenbase.org), the model organism database for Xenopus laevis and X. (Silurana) tropicalis, is the principal centralized resource of genomic, development data and comm...
Jeff B. Bowes, Kevin A. Snyder, Erik Segerdell, Ch...
119
Voted
APCSAC
2006
IEEE
15 years 8 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
CDES
2006
149views Hardware» more  CDES 2006»
15 years 3 months ago
Crosstalk at the Dynamic Node of Domino CMOS Circuits
- The need for faster circuits in smaller area with lower power dissipation has made it a common practice to use the domino CMOS in high performance integrated circuits. However th...
Waleed Al-Assadi, Vipin Sharma, Pavankumar Chandra...