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91
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ASPDAC
2006
ACM
148views Hardware» more  ASPDAC 2006»
15 years 7 months ago
An automated design flow for 3D microarchitecture evaluation
- Although the emerging three-dimensional integration technology can significantly reduce interconnect delay, chip area, and power dissipation in nanometer technologies, its impact...
Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Re...
116
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BMCBI
2008
154views more  BMCBI 2008»
15 years 2 months ago
Bayesian models and meta analysis for multiple tissue gene expression data following corticosteroid administration
Background: This paper addresses key biological problems and statistical issues in the analysis of large gene expression data sets that describe systemic temporal response cascade...
Yulan Liang, Arpad Kelemen
FCCM
2000
IEEE
114views VLSI» more  FCCM 2000»
15 years 6 months ago
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
Fault tolerance is becoming an increasingly important issue, especially in mission-critical applications where data integrity is a paramount concern. Performance, however, remains...
Steven K. Sinha, Peter Kamarchik, Seth Copen Golds...
ISMS
2004
Springer
15 years 7 months ago
An Interactive Parallel Multigrid FEM Simulator
Physically based modeling of deformable objects such as cloth or human tissue has grown to be very important for virtual simulations. However, interactive simulation of these nonl...
Xunlei Wu, Tolga Goktekin, Frank Tendick
TVLSI
2010
14 years 8 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li