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» An interconnection architecture for micropayment systems
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CODES
2007
IEEE
15 years 6 months ago
Performance modeling for early analysis of multi-core systems
Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems...
Reinaldo A. Bergamaschi, Indira Nair, Gero Dittman...
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 6 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
ISCA
2002
IEEE
174views Hardware» more  ISCA 2002»
14 years 11 months ago
Efficient Task Partitioning Algorithms for Distributed Shared Memory Systems
In this paper, we consider the tree task graphs which arise from many important programming paradigms such as divide and conquer, branch and bound etc., and the linear task-graphs...
Sibabrata Ray, Hong Jiang
CCGRID
2008
IEEE
15 years 6 months ago
MPI Collectives on Modern Multicore Clusters: Performance Optimizations and Communication Characteristics
The advances in multicore technology and modern interconnects is rapidly accelerating the number of cores deployed in today’s commodity clusters. A majority of parallel applicat...
Amith R. Mamidala, Rahul Kumar, Debraj De, Dhabale...
DAGSTUHL
2004
15 years 1 months ago
Language Engineering in Practice
ns to define the abstract modelling language that determines the structure of the models that are to be used a two-step meta-modelling approach turned out as most adequate. In the ...
Martin Große-Rhode