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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 5 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
SAMOS
2004
Springer
15 years 5 months ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
CAL
2008
14 years 12 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
DAC
2005
ACM
16 years 22 days ago
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trad
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...
Andrey V. Zykov, Elias Mizan, Margarida F. Jacome,...
FIT
2010
14 years 6 months ago
A survey of services placement mechanisms for future mobile communication networks
Mobile communication networks experience a tremendous growth. According to the vision of Wireless World Research Forum (WWRF), there will be 7 trillion wireless devices serving 7 ...
Shahzad Ali, Andreas Mitschele-Thiel, Ali Diab, Am...