443 search results - page 68 / 89 » An interconnection architecture for micropayment systems |
CONEXT
2008
ACM
15 years 1 months ago
2008
ACM
Modern commodity hardware architectures, with their multiple multi-core CPUs and high-speed system interconnects, exhibit tremendous power. In this paper, we study performance lim...
HICSS
2003
IEEE
15 years 5 months ago
2003
IEEE
The current IETF standardization work has highlighted the feasibility of providing the users with a QoS network architecture in the framework of Integrated Services over Different...
DFT
2005
IEEE
15 years 5 months ago
2005
IEEE
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
134
click to vote
FPGA
2003
ACM
15 years 5 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
SCS
2004
15 years 1 months ago
2004
Limitations in scope but also difficulties with the efficiency and scalability of present algorithms seem to have so far limited the industrial uptake of existing automated FMEA t...