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» An iterative logarithmic multiplier
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DSD
2003
IEEE
69views Hardware» more  DSD 2003»
15 years 2 months ago
A VLIW Architecture for Logarithmic Arithmetic
The Logarithmic Number System (LNS) is an alternative to IEEE-754 standard floating-point arithmetic. LNS multiply, divide and square root are easier than IEEE-754 and naturally ...
Mark G. Arnold
76
Voted
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 3 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
78
Voted
ARITH
2009
IEEE
15 years 4 months ago
A 32-bit Decimal Floating-Point Logarithmic Converter
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the digit-recurrence algorithm. The converter can calc...
Dongdong Chen, Yu Zhang, Younhee Choi, Moon Ho Lee...
SACRYPT
2001
Springer
110views Cryptology» more  SACRYPT 2001»
15 years 1 months ago
Random Walks Revisited: Extensions of Pollard's Rho Algorithm for Computing Multiple Discrete Logarithms
This paper extends the analysis of Pollard’s rho algorithm for solving a single instance of the discrete logarithm problem in a finite cyclic group G to the case of solving more...
Fabian Kuhn, René Struik
TC
2008
14 years 9 months ago
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems
A unified computation method of vector and elementary functions is proposed for handheld 3D graphics systems. It unifies vector operations like vector multiply, multiply-and-add, d...
Byeong-Gyu Nam, Hyejung Kim, Hoi-Jun Yoo