Sciweavers

65 search results - page 8 / 13
» An on Chip ADC Test Structure
Sort
View
57
Voted
DATE
2008
IEEE
66views Hardware» more  DATE 2008»
15 years 5 months ago
Optimal Margin Computation for At-Speed Test
— In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly highe...
Jinjun Xiong, Vladimir Zolotov, Chandu Visweswaria...
DATE
2002
IEEE
117views Hardware» more  DATE 2002»
15 years 4 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
15 years 5 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
ISVLSI
2007
IEEE
181views VLSI» more  ISVLSI 2007»
15 years 5 months ago
Code-coverage Based Test Vector Generation for SystemC Designs
Abstract— Time-to-Market plays a central role on System-ona-Chip (SoC) competitiveness and the quality of the final product is a matter of concern as well. As SoCs complexity in...
Alair Dias Jr., Diógenes Cecilio da Silva J...
GLVLSI
2002
IEEE
108views VLSI» more  GLVLSI 2002»
15 years 4 months ago
Protected IP-core test generation
Design simplification is becoming necessary to respect the target time-to-market of SoCs, and this goal can be obtained by using predesigned IP-cores. However, their correct inte...
Alessandro Fin, Franco Fummi