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ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 5 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...
CASES
2000
ACM
15 years 5 months ago
Flexible instruction processors
This paper introduces the notion of a Flexible Instruction Processor (FIP) for systematic customisation of instruction processor design and implementation. The features of our app...
Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
DFG
2007
Springer
15 years 8 months ago
Comparative Tensor Visualisation within the Framework of Consistent Time-Stepping Schemes
: Nowadays, the design of so-called consistent time-stepping schemes that basically feature a physically correct time integration, is still a state-of-the-art topic in the area of ...
Rouven Mohr, Tom Bobach, Younis Hijazi, Gerd Reis,...
SASN
2004
ACM
15 years 7 months ago
Resilient aggregation in sensor networks
This paper studies security for data aggregation in sensor networks. Current aggregation schemes were designed without security in mind and there are easy attacks against them. We...
David Wagner
EURODAC
1994
IEEE
120views VHDL» more  EURODAC 1994»
15 years 5 months ago
Generating compilers for generated datapaths
Modern CAD systems allow the designers to come up with powerful programmable datapaths in avery short time. The time to develop compilers for this datapaths is much longer. This p...
Michael Held, Manfred Glesner