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» An operational happens-before memory model
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ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
14 years 9 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
15 years 3 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
POPL
2010
ACM
15 years 7 months ago
On the Verification Problem for Weak Memory Models
We address the verification problem of finite-state concurrent programs running under weak memory models. These models capture the reordering of program (read and write) operation...
Ahmed Bouajjani, Madanlal Musuvathi, Mohamed Faouz...
TPHOL
2009
IEEE
15 years 4 months ago
A Better x86 Memory Model: x86-TSO
Abstract. Real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory mode...
Scott Owens, Susmit Sarkar, Peter Sewell
VLDB
2002
ACM
143views Database» more  VLDB 2002»
14 years 9 months ago
SQL Memory Management in Oracle9i
Complex database queries require the use of memory-intensive operators like sort and hashjoin. Those operators need memory, also referred to as SQL memory, to process their input ...
Benoît Dageville, Mohamed Zaït