3120 search results - page 26 / 624 » An optimal architecture for a DDC |
IPPS
1996
IEEE
15 years 2 months ago
1996
IEEE
Multiple instruction issue processors place high demands on register file bandwidth. One solution to reduce this bottleneck is the use of multiple register files. Register allocat...
CODES
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
ARC
2008
Springer
14 years 12 months ago
2008
Springer
Abstract. This paper presents a novel dynamically reconfigurable hardware architecture for lossless compression and its optimization for space imagery. The proposed system makes us...
DATE
2005
IEEE
14 years 12 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
DAC
2000
ACM
15 years 2 months ago
2000
ACM
