3120 search results - page 30 / 624 » An optimal architecture for a DDC |
DAC
1997
ACM
15 years 2 months ago
1997
ACM
We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP...
DAC
1994
ACM
15 years 2 months ago
1994
ACM
New placement techniques are presented which substantially improve the process of automatic layout generation of analog IC's. Extremely tight specifications can be enforced o...
DAC
1995
ACM
15 years 1 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
DAC
2010
ACM
14 years 11 months ago
2010
ACM
In this study, we propose the use of specialized influence models to capture the dynamic behavior of a Network-onChip (NoC). Our goal is to construct a versatile modeling framewor...
CDC
2008
IEEE
14 years 10 months ago
2008
IEEE
Novel event-triggered sensing and actuation strategies are presented for networked control systems with limited communication resources. Two architectures are considered: one with ...