3120 search results - page 32 / 624 » An optimal architecture for a DDC |
VTS
1998
IEEE
15 years 2 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
DAC
1994
ACM
15 years 2 months ago
1994
ACM
- This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. We focus on behavioral specifications with mutually exclusive pa...
DAC
1994
ACM
1994
ACM
Performance Analysis and Optimization of Schedules for Conditional and Loop-Intensive Specifications
15 years 2 months ago
This paper presents a new method,based on Markov chain analysis, to evaluate the performance of schedules of behavioral specifications. The proposed performance measure is the expe...
DAC
2005
ACM
14 years 12 months ago
2005
ACM
Layout parasitics have great impact on analog circuit performance. This paper presents an algorithm for explicit parasitic control during layout retargeting of analog integrated c...
DAC
2011
ACM
13 years 9 months ago
2011
ACM
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed based on the proposed coupling model. Analysis results show that TSVs cause significan...