3120 search results - page 45 / 624 » An optimal architecture for a DDC |
ICASSP
2011
IEEE
14 years 1 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
FPGA
2004
ACM
15 years 1 months ago
2004
ACM
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
ECOOP
1998
Springer
15 years 2 months ago
1998
Springer
In this paper, we propose architectural support for object manipulation, stack processing and method invocation to enhance the execution speed of Java bytecodes. First, a virtual a...
ASPDAC
2007
ACM
15 years 2 months ago
2007
ACM
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
CIBCB
2007
IEEE
15 years 2 months ago
2007
IEEE
-- A large and reliable DNA codeword library is the key to the success of DNA based computing. Searching for the set of reliable DNA codewords is an NP-hard problem, which can take...