3120 search results - page 51 / 624 » An optimal architecture for a DDC |
140
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PDP
2011
IEEE
14 years 4 months ago
2011
IEEE
Abstract—The peer-to-peer networking concept has revolutionized the cost structure of Internet data dissemination by making large scale content delivery with low server cost feas...
109
Voted
DAC
2011
ACM
14 years 11 days ago
2011
ACM
SRAM design has been a major challenge for nanoscale manufacturing technology. We propose a new bit cell repair scheme for designing maximum-information memory system (MIMS). Unli...
111
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DAC
2012
ACM
13 years 3 months ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
96
Voted
ASAP
1997
IEEE
15 years 4 months ago
1997
IEEE
This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus i...
86
Voted
TEC
2008
15 years 14 days ago
2008
Abstract--In previous research, we have designed and successfully tested a Traffic Light Cycles Evolutionary Optimization Architecture. In this paper, we attempt to validate those ...