3120 search results - page 62 / 624 » An optimal architecture for a DDC |
166
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ISJGP
2010
14 years 10 months ago
2010
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
86
Voted
IPPS
1998
IEEE
15 years 4 months ago
1998
IEEE
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
117
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GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
112
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FCCM
2009
IEEE
15 years 4 months ago
2009
IEEE
FPGA has long been considered an attractive platform for high performance implementations of string matching. However, as the size of pattern dictionaries continues to grow, such ...
125
Voted
ICCAD
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper addresses the design of multi-mode architectures for digital signal processing applications. We present a dedicated design flow and its associated high-level synthesis t...