3120 search results - page 63 / 624 » An optimal architecture for a DDC |
118
Voted
ICCD
2007
IEEE
15 years 4 months ago
2007
IEEE
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
77
Voted
DATE
2004
IEEE
15 years 4 months ago
2004
IEEE
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
115
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CSE
2009
IEEE
15 years 4 months ago
2009
IEEE
Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architectur...
121
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AIPR
2008
IEEE
15 years 2 months ago
2008
IEEE
In this paper, we introduce real time image processing techniques using modern programmable Graphic Processing Units (GPU). GPUs are SIMD (Single Instruction, Multiple Data) device...
111
Voted
EVOW
2008
Springer
15 years 2 months ago
2008
Springer
The design of computer architectures requires the setting of multiple parameters on which the final performance depends. The number of possible combinations make an extremely huge ...