3120 search results - page 64 / 624 » An optimal architecture for a DDC |
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CPHYSICS
2010
15 years 21 days ago
2010
In this paper, a programming model is presented which enables scalable parallel performance on multi-core shared memory architectures. The model has been developed for application...
ANCS
2009
ACM
14 years 10 months ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
89
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LCPC
1999
Springer
15 years 4 months ago
1999
Springer
The traditional target machine of a parallelizing compiler can execute code sections either serially or in parallel. In contrast, targeting the generated code to a speculative para...
124
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ISCA
1998
IEEE
15 years 4 months ago
1998
IEEE
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
102
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ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...