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ISQED
2008
IEEE
120views Hardware» more  ISQED 2008»
15 years 4 months ago
Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...
Huifang Qin, Animesh Kumar, Kannan Ramchandran, Ja...
ISQED
2010
IEEE
170views Hardware» more  ISQED 2010»
15 years 2 days ago
New SRAM design using body bias technique for ultra low power applications
A new SRAM design is proposed. Body biasing improves the static noise margin (SNM) improved by at least 15% compared to the standard cells. Through using this technique, lowering ...
Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Yn...
JOLPE
2008
110views more  JOLPE 2008»
14 years 10 months ago
Multi-Threshold Asynchronous Circuit Design for Ultra-Low Power
Andrew Bailey, Ahmad Al Zahrani, Guoyuan Fu, Jia D...