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» An ultra-fast instruction set simulator
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JSA
2007
152views more  JSA 2007»
15 years 1 months ago
Asynchronous arbiter for micro-threaded chip multiprocessors
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. T...
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
CODES
2007
IEEE
15 years 8 months ago
HySim: a fast simulation framework for embedded software development
Instruction Set Simulation (ISS) is widely used in system evaluation and software development for embedded processors. Despite the significant advancements in the ISS technology,...
Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leu...
WSC
2007
15 years 4 months ago
Simulation 101 software: workshop and beyond
The C source code associated with the Simulation 101 preconference workshop (offered at the 2006 and 2007 Winter Simulation Conferences) is presented here. This paper begins with ...
Barry Lawson, Lawrence Leemis
DATE
2009
IEEE
111views Hardware» more  DATE 2009»
15 years 8 months ago
Increased accuracy through noise injection in abstract RTOS simulation
RTOS Simulation Henning Zabel, Wolfgang Mueller Universität Paderborn, C-LAB Fürstenallee 11, D-33102 Paderborn, Germany —Today, mobile and embedded real-time systems have to c...
Henning Zabel, Wolfgang Mueller
ISPASS
2005
IEEE
15 years 7 months ago
Simulation Differences Between Academia and Industry: A Branch Prediction Case Study
Computer architecture research in academia and industry is heavily reliant on simulation studies. While microprocessor companies have the resources to develop highly detailed simu...
Gabriel H. Loh