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» An ultra-fast instruction set simulator
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DATE
2008
IEEE
110views Hardware» more  DATE 2008»
15 years 8 months ago
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set
One of the upcoming challenges in embedded processing is to incorporate an increasing amount of adaptivity in order to respond to the multifarious constraints induced by today’s...
Lars Bauer, Muhammad Shafique, Stephanie Kreutz, J...
CHES
2009
Springer
150views Cryptology» more  CHES 2009»
15 years 8 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
WSC
1997
15 years 3 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
ACL
2006
15 years 3 months ago
Semantic Discourse Segmentation and Labeling for Route Instructions
In order to build a simulated robot that accepts instructions in unconstrained natural language, a corpus of 427 route instructions was collected from human subjects in the office...
Nobuyuki Shimizu
ICCD
2006
IEEE
185views Hardware» more  ICCD 2006»
15 years 11 months ago
An accurate Energy estimation framework for VLIW Processor Cores
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...
Sourav Roy, Rajat Bhatia, Ashish Mathur