189 search results - page 7 / 38 » An ultra-fast instruction set simulator |
ASPDAC
2006
ACM
15 years 8 months ago
2006
ACM
– An instruction set level reference model was developed for the development of synergistic processing unit (SPU) , which is one of the key components of the cell processor [1][2...
133
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TCAD
2002
15 years 1 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
112
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MICRO
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
102
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ICCAD
1997
IEEE
15 years 6 months ago
1997
IEEE
We developed a new hierarchical modular approach for synthesis of area-minimal core-based data-intensive systems. The optimization approach employs a novel global least-constraini...
124
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RSP
2003
IEEE
15 years 7 months ago
2003
IEEE
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...