1565 search results - page 12 / 313 » An unlikely result |
VTS
2003
IEEE
15 years 5 months ago
2003
IEEE
Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimizati...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
DATE
2002
IEEE
15 years 4 months ago
2002
IEEE
We propose a novel approach to bus energy minimization that targets crosstalk effects. Unlike previous approaches, we try to reduce energy through capacitance optimization, by ad ...
ICLP
2001
Springer
15 years 4 months ago
2001
Springer
In the paper we establish the xed-parameter complexity for several parameterized decision problems involving models, supported models and stable models of logic programs. We also e...
ICCAD
1999
IEEE
15 years 4 months ago
1999
IEEE
A common approach to performance optimization of circuits focuses on re-synthesis to reduce the length of all paths greater than the desired delay . We describe a new delay optimi...